EDA News Monday December 8, 2003 From: EDACafe ÿÿ Previous Issues _____ Cadence _____ About This Issue A Day in the Life Heaven hath no fury like an editor on deadline _____ December 1 - 5, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Thursdays are never good around here. I'm always on deadline, grumpy, and short on patience. I shouldn't accept phone calls or agree to go out and see companies. I should know better. Today's Thursday, but I went out nonetheless. I attended a small luncheon hosted by a big company for a small handful of editors. There were nice sandwiches, fresh coffee, and a selection of salads. There were nice people in a nice conference room sitting around a nice table, with the potential for nice conversation. The editors all got a nice gift when it was over. What could be nicer? But it's Thursday. I was grumpy at lunch and grumpy all the way back to the office. I still am. The article I had hoped to run in this space isn't finished. In lieu of that article, I'm going to share the basic flow of the conversation at lunch. The conversation around the table, before and during lunch, wandered from topic to topic - the editors discussing things between themselves, with an occasional verbal nod from our hosts. Eventually our hosts guided the conversation around to laying out some of their technology initiatives for next year. They also invited questions and feedback. Here's roughly how the conversation went. This is the cleaned-up version. The darker version is a lot grumpier. Why do engineers over the age of 35 often prove ineffective, or even unemployable? They are 10 to 12 years out of school, increasingly obsolete, and usually replaced by younger, cheaper, and smarter engineers. Companies don't want to pay the price of keeping more senior engineers on board. What are older engineers to do? They should enroll in their closest on-line university, quickly earn an MBA, and hope they can salvage their career by transitioning over into a management track. What happens to companies when all of their engineers are young, without a history in the industry or in the company? The company - and the industry - loses its corporate/technical memory and becomes, in the long run, more and more ineffectual. Everybody has to re-invent the wheel over and over again, because anybody who had previously invented the wheel is no longer with the company. The development process is less efficient and more reliant on outside consultants who are hired project by project, further emphasizing the lack of continuity and long-term in-house expertise. It's been particularly bad for engineers in this last 3 years, which has been absolutely brutal due to the downturn. Companies have lost a lot of in-house expertise and are now putting more and more of the burden on the vendors and tools suppliers to provide expertise for tools usage. What was it like in the 'before' time? It used to be that a company would encourage you to get your Ph.D., to pursue advanced technical expertise. But as companies began to go more and more public, companies began to treat their engineers more and more like Kleenex - as something disposable. The companies said their older engineers simply weren't needed anymore. But can't companies see that they're losing a lot by letting go of their seasoned engineers? Not really. They see that the younger engineers work 60-hour work weeks. The old guys only want to work 40. What the companies don't see is that the older engineers know what they're doing, so that in their 40 hours they're accomplishing as much, if not more, than the younger guys are in 60 - the younger guys who are still learning their craft. Are we mostly talking about Digital Engineers here? You betcha. Digital design is a young man's game. It's a short life - but a merry one. What ever happened to the Product Engineer? This was the guy who had a larger perspective on things. He (or she) had a good grasp of physics and chemistry and engineering and business issues simultaneously, and could understand the full implications of design decisions, and how those decisions impacted things up and down the design-to-manufacture-to-test-to-market chain. That guy no longer exists - fault the universities for failing to turn out these kinds of people. Today's engineers know more and more about less and less. Product Engineers may be a thing of that past, but what about Analog Engineers? Yeah, nothing's changed there. The analog guys still continues to do the black magic. They're still very much in demand. What are companies in the semiconductor industry worried about right now? Many things, particularly yield. Why? Because even though some people have made the move to 90 nanometers, their yields are proving to be no better, functionally, than at 180 nanometers - it costs more at 90 nanometers, but the yields are no better. Also at 10 layers of metal or more, there are so many processing steps required, there's all that much more room for error, expense, and difficulty. Also, many semiconductor companies are still waffling around between high and low-k dielectrics. What's being done about it? Our luncheon hosts offered - one thing that would help is to facilitate knowledge sharing across the food chain, so that Test can talk to Manufacturing can talk to Design. The editors were not starry eyed at the prospects. The editors said that there's little motivation on the part of many of the parties in the food chain - in particular, the foundries - to share process data back up stream to facilitate yield, or ease of design. The foundries often see this data as proprietary and don't perceive any benefit from sharing this information. Our hosts said that everybody wants to get along. The editors shifted around in their chairs. Isn't packaging an issue today? It sure as heck is - the package is now part of the design, part of the overall circuitry. There are now, and will continue to be, a host of issues surrounding package development and integrity. Packaging is hot. So besides yield and packaging issues, what else is a big problem for customers today? Time-to-market. Same old. Same old. All the editors around the table nodded. It's always time to market. Even though your gut instinct might drive you to conclude that things have changed in the downturn, it's still all about hitting that market window. End of story. So now you're still in a pickle. You need to hit your market window. But you also need to make your product bug free. What's a company to do? Kick the product out the door on time and hope that your end-user doesn't end up debugging the thing for you - or worse yet, hope that your end-user doesn't go away mad and find some other supplier next time around. Why is this any different than it's always been - hasn't it always been an optimization problem? Yeah, you try to find the right cross-over point that maximizes quality and minimizes time-to-market. There's nothing new under the sun there. The topic changed - isn't strategic partnering with companies a difficult thing? Our hosts said that partnering is now, and has always been, very important to them. Partnering is a delicate business, one that requires finesse and a mature understanding of the different nuances across companies and cultures. How do you deal with 'partners' who refuse to show partiality towards your company's technology? Our hosts said that dealing with partners who are aggressively neutral can be very challenging. What are you doing in the FPGA space? Our hosts said they don't really see any way to make money in the FPGA space. Structured ASICs, however, are a different story. Really? A lot of people may not agree with you on that FGPA thing. Our hosts asked the editors to explain to them how one makes money in the FPGA space. One editor said that these days the FGPA guys are discovering they can't afford to develop and support tools to enhance their product usage. Maybe that was the clue. Our hosts said they still don't see much of a market there. Are you concerned about expanding into markets like China where your IP is potentially compromised? Our hosts said they have few concerns, if any. It's companies like ARM who should be worried. After all, the GDS of a core is more easily compromised than design tools. One editor said why worry about tools being pirated when you can buy copies of anybody's software in any subway in Moscow. Our hosts reiterated that it's companies like ARM that should be the ones that are worried. What's the news in design services these days? Our hosts said that their design services are pushing the cutting-edge designs, leading the industry into next-generation technologies. Does that mean that you end up competing with your customers? Our hosts said not at all. At 90 nanometers, the challenges are so great, customers welcome the help. If the customers need that much help, doesn't it reflect poorly on the ease-of-use of your tools? An editor at the table answered that one and said that these days the customers, particularly the fabless guys, are so short on staff - they've laid off so many people - that they've become completely reliant on the tool vendors to provide not only software, but also help with applying the software to new problems. That's the reality today. Our hosts agreed. Our hosts said politely that anyway the point of the luncheon was not for them to be grilled about things, but for all of us to get to know one another. The editors politely agreed. We all stood up, received our gifts, shook hands, and left. I drove to the office. I typed this up. I stared out the window at the rain and the deepening gloom. I thought abut editors and how once they accept food and beverage, gifts and favors, their ability to be objective is compromised - possibly critically so. I thought about companies and executives and politicians who, not surprisingly, would rather spend time building bridges with members of the press who are not perceived to be predisposed against the company, the executive, or the politician. I wondered how the Bush administration picked those particular journalists to accompany the President on his Thanksgiving trip to Baghdad. I wondered how our hosts today chose those particular journalists to attend the luncheon. I wondered how people so quickly forget that it's in the best interest of the company, the executive, the politician, and the journalist, to maintain an adversarial relationship between the entity and the press corps that covers them. I wondered why editors are just as human as the rest of them - falling prey to opportunities to pontificate and pronounce. Why editors are so endearingly full of themselves. Why executives are so endearingly full of themselves, except when they're being self-effacing to endear themselves to the press. I wondered if those who are not in the press ever understand how deeply cynical those in the press eventually become. And that the food and beverage, gifts and favors, only make them more so. I thought about the closing scene of "Inherit the Wind." I thought about Clarence Darrow and William Jennings Bryon and the reporter that covered the trial. I wondered if it's only the foolish and the old that truly believe. I wondered if the members of the press are ever foolish or old. I turned back to my desk. I saw the gift I had received lying there next to my keyboard. I opened the gift. It was a wallet and key chain. Or was it, in truth, a ball and chain. I turned off the computer and stood up to leave. I noticed that the gloom of dusk had given way to the dark of night. Industry News - Tools and IP Accelerated Technology, a division of Mentor Graphics Corp, announced mass storage class driver support for the Nucleus USB software, which provides USB support for the Nucleus RTOS. The company also announced the release of the Nucleus RTOS for the S1C33209 32-bit RISC processor from Seiko Epson Corp. The company says this release will give developers using the S1C33209 a "complete, full-featured RTOS to address the high-performance needs of building cellular, digital consumer and PC peripheral applications." Applied Wave Research, Inc. (AWR) announced that the company's Analog Office, Visual System Simulator, and Microwave Office design suites will be available on the Linux platform in Q1 2004. James Spoto, CEO and President of AWR, is quoted in the Press Release: "The advantages of Linux complement AWR's innovative and open technology by dramatically reducing product development time. We believe that the many attributes of Linux, including operating stability, security, performance, and interoperability with both UNIX and Windows platforms, will provide designers with a viable and cost-effective alternative." Also per the Press Release: "AWR's existing and prospective customers are demanding support for the Linux operating system, which users believe is less expensive and complicated to operate and support than UNIX, while providing better security and administration than Windows 2000/XP. This is especially true in the Asia Pacific region and other emerging electronic design markets, where UNIX is not a legacy system. In addition, as more industry-leading EDA tools and design flows are now being offered on the Linux platform, AWR will be able to provide a better and more complete design flow for its customers." Carbon Design Systems announced the general availability of its SPEEDCompiler and DesignPlayer tool suites aimed at pre-silicon system validation, where "thousands of users can simultaneously develop and test software on the 'golden' RTL hardware implementation model." SPEEDCompiler software reads Verilog RTL and generates an ultra-high performance linkable object representation that is both cycle and register accurate. The object includes a 'C' API for system integration and an interrogation manager for design debug. The DesignPlayer engine incorporates a SPEEDCompiler object to create a deployable runtime model of a chip or an IP block - at the system level, DesignPlayer engines can represent multiple chips. Carey McMaster, Director of Software Engineering at StarGen, is quoted in the Press Release: "We wanted to employ RTL hardware models for software driver validation, but hit a simulation wall of 8 days per iteration. DesignPlayer reduced our validation turn-time from 8 days to 8 minutes and performed distributed discovery on a 20 node switch fabric that encompassed over 15 million gates." CoWare Inc. announced the addition of Ultra Wideband (UWB) to its Signal Processing Worksystem (SPW) wireless LAN library. The company says it is the first in the industry to announce library support for the technology being considered for the emerging UWB standard. Per the Press Release: "Two proposals are under consideration for the standard of implementing UWB in short- range wireless personal area networks. The CoWare SPW wireless LAN library now supports orthogonal frequency-division multiplexing (OFDM) technology. If the competing proposal for direct sequence code division multiple access (DSCDMA) technology is accepted, CoWare will expand its WLAN library to support it as well." Denali Software, Inc. and StarGen, Inc. announced a collaborative effort to ensure interoperability of products which use the Advanced Switching (AS) interconnect. StarGen engineers say they have selected Denali's PureSpec verification IP to simulate, and verify compliance and interoperability of the AS interface in StarGen's StarXpress product line. Denali say it has extended its PureSpec product platform to allow StarGen and other AS chip developers to create and exchange simulation models of their AS interfaces under development, and simulate the interaction between their designs early in the development cycle. Hier Design Inc. announced enhancements to its hierarchical floorplanning and analysis software. The company says its PlanAhead software is an "effective solution" for automating the design and integration of IP blocks within FPGAs, which should help designers to create FPGA prototypes quickly to verify ASIC designs. Per the Press Release: "The PlanAhead software has been enhanced to automate the importing and exporting of IP blocks with their VHDL and Verilog shells, as well as the creation of relatively placed macros (RPMs) for Xilinx FPGAs." Intellitech Corp. announced availability of the PTC (Parallel Test & Configuration), which the company says is an addressable 1149.1 gateway device. Per the Press Release: "The PTC IC is designed into what is called 'blade' PCBs, boards designed to plug into a multi-slot or multi-cabled backplane. It provides the infrastructure necessary for multi-PCB FPGA configuration and system PCB to PCB interconnect test. It is a key element in designing multi-PCB systems that can perform in-the-field upgrades to all of the non-volatile devices of the system. It's also a necessary element for performing tests of PCB to PCB gigabit SERDES and LVDS connections and diagnosing connection problems to the pin. It can be used on blades targeted for proprietary telecomm backplanes or on PCBs used in standard backplanes such as cPCI, VME and VXI." Complex stuff. Legend Design Technology, Inc. announced that Fujitsu/Fujitsu VLSI has adopted Legend's CharFlo-Memory! to characterize embedded memory instances for SRAM and ROM compilers. The company says the CharFlo-Memory! toolset is based on layout-extracted circuit data with resistors and capacitors and has the capacity to generate accurate on-chip memory instance models at any PVT (process, voltage and temperature) corner. Yasuhiko Maki, Manager of Advanced LSI Development Division Advanced CMOS Technology Department at Fujitsu, is quoted: "To provide accurate simulation models, we use Legend's memory characterization tool, CharFlo-Memory!, to quickly produce models that reflect the reality of the silicon." Mentor Graphics Corp. introduced Precision Physical Synthesis, which the company says is the first integrated RTL and physical FPGA synthesis tool that addresses the productivity and timing closure challenges associated with complex programmable devices. Per the Press Release: "The Precision Physical Synthesis product defines a new approach to FPGA synthesis with an RTL-to-placed-gates solution, built on a single data model, that simultaneously optimizes gate and interconnect delay to shave weeks to months off a product design cycle. The highly productive design environment integrates seamlessly into the comprehensive Mentor Graphics FPGA tool flow, and is the continuation of a FPGA technology roadmap." Also from Mentor Graphics - The company announced it has established a joint marketing agreement with PCBstandards.com, Inc., a supplier of CAD libraries and library tools, to make the PCBstandards.com, Inc. library available for use with Mentor Graphics PADS product line. The companies say, "The library contains all of the land patterns found in the IPC-SM-782 specification, in the PADS PowerPCB format." Neolinear, Inc. announced that their collaboration with Renesas Technology Corp. has resulted in a design win for Renesas. The companies say that over the past year, Renesas and Neolinear have been working in conjunction with Neolinear's Japanese distributor Cadence Design Systems, Japan, to build a "next generation analog design flow to enable Renesas designers to bring their designs to market on time, against extremely aggressive design schedules." Toshiyasu Akiyama, Department Manager, Analog EDA Technology Development Department, LSI Product Technology Unit, Renesas Technology Corp., (can that all fit on one business card?), is quoted in the Press Relase: "The business pressure to shorten design cycles is intense. At Renesas, my group took the initiative to overhaul our design flow and make it best in class to ensure we could meet our business goals. Partnering with Neolinear to incorporate NeoCell into our methodology has given us the necessary productivity boost we were looking for to stay ahead of the competition." Novas Software, Inc. has introduced the Reusner Design Knowledge Publisher and a "smart reuse" methodology. The company says that the product and methodology allow in-house design teams and third-party IP providers to electronically publish critical design knowledge for debug and product documentation of IC designs, IP components, reusable design blocks and SoC platforms. Per the Press Release: "Design understanding and knowledge are crucial to design success, especially as companies move to more complex SoC technologies and methodologies. But often, important knowledge is lost, missing, or inaccessible due to ad hoc documentation processes and the widening gap across time and distance within distributed design organizations. Legacy designs or third-party IP blocks can be especially difficult to understand because of limited access to the original creators or other experts. For external IP, the ability to transfer design and integration knowledge has direct technical and business implications for both IP providers and consumers." "Reusner is based on the same Design Knowledge Architecture (compilers, databases) as Novas' core debug systems. In addition, Reusner utilizes an entirely new visualization engine that drives the generation of documentation-quality block diagrams, schematics and finite state machine bubble diagrams. This new topology-driven visualization engine also has built-in synchronization control to ensure that design views are always current. Reusner instantly recreates saved design views as they are opened, combining the stored visual topologies with the connectivity extracted from the latest design information. HDL source code changes are therefore automatically reflected in the updated view. Reusner views are catalogued in reusable electronic design notebooks for easy access using intuitive search, query and recall utilities. These provide an effective mechanism for communicating design intent between those who create design blocks and those who verify or reuse them." ReShape Inc. announced that physical designers using design tools from Cadence Design Systems Inc. can now use ReShape's automated chip construction tool, PD Builder, to realize flat layout quality for complex SoCs. The company says, "Combined with ReShape's PD Optimizer hierarchical optimization tool, PD Builder fully automates and parallelizes the process of chip construction and verification. ReShape's Cadence Flowlib Library enables Cadence physical design tool users to take advantage of ReShape's SoC optimization technology." I spoke briefly by phone with Bob Dahlberg, Vice President of Business Development at Reshape, regarding the announcement. He told me: "The company is attacking a fundamental problem associated with doing SoC design - chip-level decisions and how you allocate resources between all the blocks. Today, people spend all their time trying to optimize all the individual blocks and most P&R tools do a pretty good job at that level. But we're attacking the problem at the chip level." "We're looking at two situations: How do you intelligently and optimally allocate resources, global interconnects and power between blocks when there's no automation there? - and -There's a need to build a chip and iterate [to a solution], but that's slow and painful. [To address these issues], currently we're attacking both the optimization of global resource and the fast iteration of chip construction. This press release is related to the later. How do you get that fast construction of chips?" "Essentially, we've come up with an approach - everybody today uses some kind of scripting to automate the tools working together, but that's an extremely difficult thing to do. One person on the team has to write an incredible amount of code to make the tools work together, it's fragile code and rarely reusable. What we've come up with is a mechanism at a higher level of abstraction that will automatically generate scripts to drive the EDA tools. It's called PD Builder and it provides support for a couple of different set of tools. It already supported Synopsys' Astro tools and now it supports the Cadence Encounter platform." "We're providing customers with a flow library, which includes pre-codified stages that are based on a set of algorithms that can automatically generate the script that will set up, execute, and extract the data from the tools. The by-product is two-fold - it speeds up the tools and it allows for simultaneously executing parallel blocks. This ability allows full-chip builds in 24 hours. A process that previously could take a week to 10 days, is now reduced to an overnight [event]. Customers like to buy best-of-breed tools [from a range of vendors], and this allows them to do that." Tensilica, Inc. announced that LG Electronics of Korea has licensed Tensilica's Xtensa microprocessor technology. LG says it will integrate the processor into an SoC for the Korean Government's newly announced Digital Multimedia Broadcasting (DMB) Standard, which includes applications such as cell phones, portable devices, and digital TVs. Jong-Seok Park, Vice President of LG, is quoted in the Press Release: "We want to be first to market with exciting new products that integrate digital multimedia for the Korean market, but we were faced with lengthening RTL hardware design cycles. By using Xtensa processors, we can cut the design time significantly, plus benefit from the programmability of the solution." Newsmakers Apache Design Solutions announced it has joined the Synopsys in-Sync interoperability program. The companies say that through the in-Sync program, Apache's RedHawk-SDL will interface with Synopsys' PrimeTime static timing analyzer. Keith Mueller, Vice President of Sales and Marketing at Apache. is quoted: "We joined the Synopsys in-Sync Program to facilitate interoperability between Apache's Red Hawk and Synopsys' PrimeTime. Apache's participation in the in-Sync program will enable our mutual customers' design flows to run more smoothly." Hier Design Inc. announced the appointment of Craig Robbins to the role of Vice President of Sales. He will assume responsibility for all worldwide sales activity and will report to Heir Design CEO Jackson Kreiter. Previously, Robbins was a Vice President at Cadence Design Systems, coming to Cadence by way of the Silicon Perspective acquisition. He has also served in executive capacities at Averant, Nevo Technologies, ATG Technology, Gateway Design Automation, Redwood Design Automation, and Parsec Software. Robbins has both an MBA and a BS in Marketing from U.C. Berkeley. LogicVision, Inc. announced the appointment of James Healy as President and CEO, effective immediately. Healy succeeds company founder Vinod Agarwal, who will serve now as Executive Chairman and Chief Strategist. Previously, Healy was President of Spriox, USA, which is a distributor of LogicVision products in "Greater China." Healy has also been President of ASAT USA, President and CEO of both Genus and Credence Systems, and an executive with FormFactor and LTX. He is the author of two books - "Automatic Testing and Evaluation of Digital Integrated Circuits" and "Winning the High Tech Sales Game." Healy has an MS from California State University at Hayward. Vinod Agarwal is quoted in the Press Release: "Jim is an excellent addition to our company. He has more than 30 years of industry experience in managing operations, engineering, sales, and marketing with a number of semiconductor equipment companies. His expertise and knowledge of our business will be invaluable as LogicVision enters its next level of growth. Jim's appointment will also provide me with the opportunity to focus more on building strategic partnerships and enhancing our technological leadership. We believe that these management changes have strengthened our executive team and will enable LogicVision to realize its full potential in the embedded test market." Sequence Design announced that Li-Fu Chang, Sequence Design Project Manager, has been named to the board of the Fabless Semiconductor Association's (FSA) Modeling Committee. Per the Press Release: "The purpose of the FSA Modeling Committee is to improve the quality of circuit models used by FSA member companies, including SPICE and interconnect models." Chang has a Ph.D. in Electrical Engineering from Purdue University. He has published/presented 35+ technical papers in journals and at conferences, and holds multiple U.S. patents. SemiView Inc. was formally launched by founders Cary Snyder, Jim Lipman, and Susan Cain as an industry analyst and information group focused on the Application-Adaptable Integrated Circuit (AAIC) industry. Snyder is Chief Analyst, Lipman is President and Editor-in-Chief, Cain is Vice President of Development and Advertisement, and Stephen Wasson is Senior Analyst and AAIC Architect for the company. The founders say the business venture is aimed at providing business, financial and technology analysis, research, and editorial information for the AAIC industry. Per the Press Release: "The types of technologies that fit within the AAIC space include configurable and reconfigurable logic and processors that utilize field-programmable hardware and/or software to reduce design cost, add function flexibility, and enable faster delivery time than traditional ASIC devices. AAIC devices offer enhanced application adaptability over traditional ASICs. Specific technology examples include FPGAs, reconfigurable microprocessors, DSPs, structured ASICs and others." SemiView is positioning itself to provide business, financial, and technology analysis, research, and editorial information for the AAIC industry. Again, per the Press Release: "SemiView will provide extensive consulting services and reports that address the needs and budgets of small, medium and large companies. SemiView will also provide hands-on product reviews, technical training, seminars, webinars, newsletters and an in-depth website. In addition, SemiView will help companies develop technical webcast or online seminar content." Jim Lipman made the following comments in a phone call on Wednesday, December 3rd: "SemiView is something that Cary and I have been talking about for a while. Cary wanted to create an information source for people and called me in [early summer] and he asked me to join him in establishing the company, and to be the president. I agreed and also brought Susan Cain on board. She has lots of good marketing and business development contacts. Cary also asked Stephen Wasson to come on-board as another analyst editor. The four of us are the core." "We will cover the AAIC market, which we consider it to be a medium-sized technology bucket. [By the way], that bucket does not include low-level EPROMs or simple MUX functions on a chip. We're only focusing on things that are substantially changeable. With SemiView, we're picking a technology niche that is cohesive, but still small enough for us to get our hands on. Some people cover ASICs, FPGAs, or DSPs - but we don't know of one organization that covers the whole AAIC space." "We want to address all the different functions that a company might need when exploring AAIC - analyst reports, papers, white papers, article development, seminars - both webcasts and live seminars - and two flavors of product evaluation. We want to be the go-between between companies with the desire, but without the resources for all of these things, and we feel that it's a very viable business model - particularly now that the market is rebounding." In the category of ... What economists do all day This one came to me by way of a friend of a friend. If you haven't seen this, it's worth a moment of your time. --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are registered as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your newsletter's details, including format and frequency, or to discontinue this service, please navigate to . If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . Copyright c 2003, Internet Business Systems, Inc. - 11208 Shelter Cove, Smithfield, VA 23420 - 888-44-WEB-44 - All rights reserved.